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| CY2XP24 Crystal to LVPECL Clock Generator Features Functional Description The CY2XP24 is a PLL (Phase Locked Loop) based high performance clock generator. It is optimized to generate 10 Gb Ethernet, Fibre Channel, and other high performance clock frequencies. It produces an output frequency that is either 6.25 times or 7.5 times the crystal frequency. It uses Cypress's low noise VCO technology to achieve less than 1 ps typical RMS phase jitter, that meets both 10Gb Ethernet, Fibre Channel, and SATA jitter requirements. The CY2XP24 has a crystal oscillator interface input and one LVPECL output pair. One LVPECL Output Pair Selectable Output Frequency: 156.25 MHz or 187.5 MHz External Crystal Frequency: 25 MHz Low RMS Phase Jitter at 156.25 MHz, using 25 MHz crystal (1.875 MHz to 20 MHz): 0.33 ps (typical) Pb-Free 8-Pin TSSOP Package Supply Voltage: 3.3V or 2.5V Commercial and Industrial Temperature Ranges Logic Block Diagram XIN External Crystal XOUT 0 = /25 1 = /30 F_SEL CRYSTAL OSCILLATOR PHASE DETECTOR VCO /4 CLK CLK# Pinouts Figure 1. Pin Diagram - 8 Pin TSSOP VDD VSS XOUT XIN Table 1. Pin Definitions - 8 Pin TSSOP Pin 1, 8 2 3, 4 5 Name VDD VSS XOUT, XIN F_SEL Power Power CMOS Input Type 1 2 3 4 8 7 6 5 VDD CLK CLK# F_SEL Description 3.3V or 2.5V power supply. All supply current flows through pin 1 Ground Frequency select. When HIGH, the output frequency is 7.5 times of the crystal frequency. When LOW, the output frequency is 6.25 times of the crystal frequency Differential clock output XTAL Output and Input Parallel resonant crystal interface 6,7 CLK#, CLK LVPECL Output Cypress Semiconductor Corporation Document #: 001-15705 Rev. *D * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised June 12, 2009 [+] Feedback CY2XP24 Frequency Table Inputs Crystal Frequency (MHz) 25 25 F_SEL 1 0 PLL Multiplier Value 7.5 6.25 Output Frequency (MHz) 187.5 156.25 Absolute Maximum Conditions Parameter VDD VIN[1] TS TJ ESDHBM UL-94 JA[2] Description Supply Voltage Input Voltage, DC Temperature, Storage Temperature, Junction ESD Protection (Human Body Model) Flammability Rating JEDEC STD 22-A114-B At 1/8 in. 1 m/s airflow 2.5 m/s airflow 2000 V-0 100 91 87 C/W Relative to VSS Non operating Condition Min -0.5 -0.5 -65 Max 4.4 VDD + 0.5 150 135 Unit V V C C V Thermal Resistance, Junction to Ambient 0 m/s airflow Operating Conditions Parameter VDD TA TPU 3.3V Supply Voltage 2.5V Supply Voltage Ambient Temperature, Commercial Ambient Temperature, Industrial Power up time for all VDD to reach minimum specified voltage (ensure power ramps are monotonic) Description Min 3.135 2.375 0 -40 0.05 Max 3.465 2.625 70 85 500 Unit V V C C ms DC Electrical Characteristics Parameter IDD[3] Description Power Supply Current with output terminated Test Conditions VDD = 3.465V, FOUT = 187.5 MHz, output terminated VDD = 2.625V, FOUT = 187.5 MHz, output terminated VOH VOL VOD1 VOD2 LVPECL Output High Voltage LVPECL Output Low Voltage LVPECL Peak-to-Peak Output Voltage Swing LVPECL Output Voltage Swing (VOH - VOL) VDD = 3.3V or 2.5V, RTERM = 50 to VDD - 2.0V VDD = 3.3V or 2.5V, RTERM = 50 to VDD - 2.0V VDD = 3.3V or 2.5V, RTERM = 50 to VDD - 2.0V VDD = 2.5V, RTERM = 50 to VDD - 1.5V Min - - VDD -1.15 VDD -2.0 600 500 Typ - - - - - - Max 150 145 VDD -0.75 VDD -1.625 1000 1000 Unit V V V V mV mV Note 1. The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required. 2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model. 3. IDD includes approximately 24 mA of current that is dissipated externally in the output termination resistors. Document #: 001-15705 Rev. *D Page 2 of 8 [+] Feedback CY2XP24 DC Electrical Characteristics (continued) Parameter VOCM VIH VIL IIH IIL CIN CINX Description Test Conditions Min 1.2 0.7*VDD -0.3 F_SEL = VDD F_SEL = VSS - -50 Typ - - - - - 15 4.5 Max - VDD + 0.3 0.3*VDD 115 - Unit V V V A A pF pF LVPECL Output Common Mode VDD = 2.5V, RTERM = 50 to VDD - Voltage (VOH + VOL)/2 1.5V Input High Voltage Input Low Voltage Input High Current Input Low Current Input Capacitance Pin Capacitance, XIN & XOUT AC Electrical Characteristics Parameter FOUT TR, TF[5] TJitter()[8] TDC[9] TLOCK Description Output Frequency Output Rise/Fall time RMS Phase Jitter (Random) Duty Cycle Startup Time 20% to 80% of full swing 156.25 MHz, (1.875-20 MHz), 3.3V Measured at zero crossing point Time for CLK to reach valid frequency measured from the time VDD = VDD(min.) or from F_SEL changing Conditions Min 156.25 - - 45 - Typ - 500 0.33 - - Max 187.5 - - 55 10 Unit MHz ps ps % ms Recommended Crystal Specifications[6] Parameter Mode F ESR C0 Mode of Oscillation Frequency Equivalent Series Resistance Shunt Capacitance Description Min 25 - - Max 25 50 7 Unit MHz pF Fundamental Notes 4. Outputs are terminated with 50 to VDD - 2V. Refer to Figure 2 on page 4 and Figure 3 on page 4. 5. Refer to Figure 7 on page 5. 6. Characterized using an 18 pF parallel resonant crystal. 7. Not 100% tested, guaranteed by design and characterization. 8. Refer to Figure 4 on page 4. 9. Refer to Figure 7 on page 5. Document #: 001-15705 Rev. *D Page 3 of 8 [+] Feedback CY2XP24 Parameter Measurements Figure 2. 3.3V Output Load AC Test Circuit 2V VDD LVPECL VSS Z = 50 SCOPE CLK 50 Z = 50 CLK# 50 -1.3V +/- 0.165V Figure 3. 2.5V Output Load AC Test Circuit 2V VDD LVPECL VSS Z = 50 SCOPE CLK 50 Z = 50 CLK# 50 -0.5V +/- 0.125V Figure 4. Output DC Parameters CLK VOD CLK# VA VOCM = (V A + VB)/2 VB Figure 5. Output Rise and Fall Time CLK# 20% TR TF 80% 80% 20% CLK Figure 6. RMS Phase Jitter Phase noise Noise Power Phase noise mark Offset Frequency f1 RMS Jitter = f2 Area Under the Masked Phase Noise Plot Document #: 001-15705 Rev. *D Page 4 of 8 [+] Feedback CY2XP24 Figure 7. Output Duty Cycle CLK TDC = CLK# TPW TPERIOD TPW TPERIOD Application Information Power Supply Filtering Techniques As in any high speed analog circuitry, noise at the power supply pins can degrade performance. To achieve optimum jitter performance, use good power supply isolation practices. Figure 8 illustrates a typical filtering scheme. Because all current flows through pin 1, the resistance and inductance between this pin and the supply is minimized. A 0.01 or 0.1 F ceramic chip capacitor is also located close to this pin to provide a short and low impedance AC path to ground. A 1 to 10 F ceramic or tantalum capacitor is located in the general vicinity of this device and may be shared with other devices. Figure 8. Power Supply Filtering V DD (Pin 8) 3.3V 0.1F 0.01 F 10F Figure 9. LVPECL Output Termination 3.3V 125 Z0 = 50 125 CLK Z0 = 50 84 IN CLK# 84 Crystal Input Interface The CY2XP24 is characterized with 18 pF parallel resonant crystals. The capacitor values shown in Figure 10 are determined using a 25 MHz 18 pF parallel resonant crystal and are chosen to minimize the ppm error. Note that the optimal values for C1 and C2 depend on the parasitic trace capacitance and are therefore layout dependent. Figure 10. Crystal Input Interface XIN VDD (Pin 1) Termination for LVPECL Output The CY2XP24 implements its LVPECL driver with a current steering design. For proper operation, it requires a 50 ohm dc termination on each of the two output signals. For 3.3V operation, this data sheet specifies output levels for termination to VDD-2.0V. This termination voltage can also be used for VDD = 2.5V operation, or it can be terminated to VDD-1.5V. Note that it is also possible to terminate with 50 ohms to ground (VSS), but the high and low signal levels differ from the data sheet values. Termination resistors are best located close to the destination device. To avoid reflections, trace characteristic impedance (Z0) should match the termination impedance. Figure 9 shows a standard termination scheme. X1 18 pF Parallel Crystal C1 30 pF Device XOUT C2 27 pF Document #: 001-15705 Rev. *D Page 5 of 8 [+] Feedback CY2XP24 Ordering Information Part Number CY2XP24ZXC CY2XP24ZXCT CY2XP24ZXI CY2XP24ZXIT 8-Pin TSSOP 8-Pin TSSOP-Tape and Reel 8-Pin TSSOP 8-Pin TSSOP-Tape and Reel Package Type Product Flow Commercial, 0C to 70C Commercial, 0C to 70C Industrial, -40C to 85C Industrial, -40C to 85C Package Drawing and Dimensions Figure 11. 8-Pin Thin Shrunk Small Outline Package (4.40 MM Body) Z8 PIN 1 ID 1 DIMENSIONS IN MM[INCHES] MIN. MAX. 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] 8 0.19[0.007] 0.30[0.012] 0.65[0.025] BSC. 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0-8 0.076[0.003] 0.85[0.033] 0.95[0.037] 2.90[0.114] 3.10[0.122] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85093-*A Document #: 001-15705 Rev. *D Page 6 of 8 [+] Feedback CY2XP24 Document History Page Document Title: CY2XP24 Crystal to LVPECL Clock Generator Document Number: 001-15705 Rev. ** *A *B ECN No. 1285703 1451704 2669117 Submission Date See ECN See ECN 03/05/2009 Orig. of Change WWZ/KVM/ New data sheet ARI WWZ/AESA Added I-temp devices KVM/AESA Changed crystal frequency and output frequencies Updated phase jitter value Rise & fall times changed from 350 ps to 500 ps (typ.) Junction temperature changed from 125C to 135C Changed IIL and IIH values Entered value for IDD Removed MSL spec Changed Data Sheet Status to Final KVM/PYRS Typos: changed VCC to VDD, changed ps to MHz Changed footnote about external power dissipation Reformatted AC and DC tables Changed LVPECL parameters from VPP to VOD and VOCM Added CINX spec Added IDD for 2.5V Added TLOCK timing Revised text in Application Information section Changed recommended crystal load capacitor values WWZ/HMT No change. Submit to ECN for product launch. Description of Change *C 2700242 04/30/2009 *D 2718433 06/12/2009 Document #: 001-15705 Rev. *D Page 7 of 8 [+] Feedback CY2XP24 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb (c) Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-15705 Rev. *D Revised June 12, 2009 Page 8 of 8 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback |
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